An interesting article on the EDACafe Blog by Vinod Viswana, R&D Director at Real Intent discussing the power of Dynamic Voltage Frequency Scaling (DVFS):

Battery life in consumer electronics is dependent on the dynamic power behavior of their integrated circuits.  If that dynamic behavior can be adjusted to fit the task at hand, then considerable power savings can be realized.  In CMOS circuits most of the dynamic power is consumed in the parasitic capacitance of their digital gates.

The equation for dynamic or transient power can be written as follows:







The combination of supply voltage and frequency has a cubic impact on total power dissipation because dynamic power consumption has a quadratic dependence on voltage and a linear dependence on frequency. An intelligent power savings solution would reduce operating frequency and, at the same time, reduce the supply voltage. Some example commercial implementations of dynamic voltage frequency scaling (DVFS) technology are Intel’s SpeedStep and AMD’s PowerNow.  According to the 2014 Calypto RTL Power Reduction Survey, 24% of designs used DVFS.

DVFS has been applied at both hardware and operating system/platform levels. The main idea is to scale the supply voltage as low as possible for a given frequency while still maintaining correct operation. The voltage can be dropped only up to a certain critical level, beyond which timing faults occur.

Some hardware mechanisms for DVFS implement timing fault detection in hardware itself using special “safe” flip flops that detect timing violations. While DVFS methods are effective in addressing the dynamic power consumption, they are significantly less effective in reducing the leakage power. As minimum feature sizes shrink, supply voltage scaling requires a reduction in the threshold voltage, which results in an exponential increase in leakage current with each new technology generation. It has been shown that the simultaneous use of adaptive body biasing (ABB) and DVFS can be used to reduce power in high-performance processors. ABB previously was used to control leakage during standby mode, and has the advantage of reducing the leakage current exponentially, whereas dynamic voltage scaling reduces leakage current linearly.

At the operating system level, several OSes now deploy some form of DVFS. For example, Linux uses a very standard infrastructure called cpu-freq to implement DVFS. Cpu-freq provides a modularized set of interfaces to manage the CPU frequency changes through various low-level, CPU-specific mechanisms and high-level system policies. Cpu-freq decouples the CPU frequency controlling mechanisms from the policies and helps in their independent development. The actual policies are implemented as “governors,” and many variations have been proposed for different kinds of systems, each with their own power and performance requirements.

Work has been done specifically at the handheld/portable/embedded systems level proposing different techniques for implementing DVFS in battery constrained devices. One such example is AutoDVS, a system for handheld computers that offers dynamic voltage scaling (DVS). AutoDVS both lowers the amount of energy used and ensures service quality by estimating user interactivity time, think-time and computation load, system-wide and for each program.

A second technique involves application-directed DVFS. It’s possible to bypass the difficult problem of trying to get good results using OS level statistics, given that not all applications behave in a predictable way. Instead, by making applications with bursty behavior power-aware, these applications can specify to the scheduler that controls clock speed and processor voltage both their average execution time and a deadline. An energy priority scheduling algorithm arranges the order for these power-aware tasks based on deadlines and the frequency of task overlap.

DVFS for multi-core processors is another interesting and challenging area. One major design decision is whether to apply DVFS at the chip level or at the per-core level. If the per-core DVFS approach is used, more than one power/clock domain per chip is needed and additional circuitry also is required for synchronization among the chips. Although per-core DVFS is more costly to implement than per-chip DVFS for single-chip multiprocessors, per-core has been reported by an academic or commercial entity to have 2.5 times better throughput. The reason is simple. A per-chip approach has to scale down the entire chip even if only a single core is starting to overheat. In contrast, a per-core approach makes only the core with a hot spot scale downward; other cores keep operating quickly unless they develop heating problems.

One question that remains open is how to manage power when running parallel/multi-threaded programs across a mixed-set of multi-core architectures – each with its own unique power and performance profile. One commercial example we can point to is ARM big.LITTLE. This approach couples slower, low-power processor cores (LITTLE) with more powerful and power-hungry ones (big). Typically, only one “side” or the other will be active at the same time. Workload can be swapped from big to LITTLE and back on the fly, because all cores have access to the same memory areas. The intent is to create a multi-core processor that can adjust better to dynamic computing needs and use less power than clock scaling alone. ARM’s marketing material promises up to a 75-percent savings in power usage for some activities.

DVFS is just one of several methods to control dynamic power consumption in CMOS circuits. While its usage brings a set of verification and implementation challenges, we will continue to see its application in future designs at both the hardware and operating system/platform levels.

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