In-Chip Monitoring Subsystem Solutions on 40nm down to 7nm

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ENHANCED CHIP RELIABILITY AND OPTIMISATION

Moortec provide highly accurate, highly featured Process, Voltage & Temperature Monitoring IP.

Support for:

  • AVS & DVFS Optimisation
  • Enhanced Reliability
  • 40nm, 28nm, 16nm & 7nm

WATCH THE EMBEDDED SUBSYSTEM VIDEO

Watch the latest Moortec In-Chip Monitoring Subsystem Solutions video and find out more about our compelling embedded subsystem IP solutions for Process, Voltage & Temperature (PVT) monitoring, targeting advanced node CMOS technologies from 40nm down to 7nm.

Latest from the Blog

04

Jun

Exploring Moortec’s In-Chip Monitoring Subsystem

What allows Moortec’s In-Chip Monitoring Subsystem to optimise the performance and reliability of advanced node SoC’s? […]

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21

May

In-Chip Performance Optimisation – Things to Consider when choosing a PVT Subsystem

With advances in CMOS technology and the scaling of transistor channel lengths down to nanometer (nm) […]

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23

Apr

Moortec support the University of Southampton ELEC6200 Group Design Project Presentation Day

On Wednesday 18th April a delegation from Moortec, including CTO Oliver King  made their way to […]

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Events


2018 TSMC Taiwan Technology Symposium 21st June, Hsinchu


2018 DAC (Design Automation Conference) 24th - 28th June, San Francisco 


2018 TSMC Japan Technology Symposium 29th June, Yokohama


2018 TSMC Europe OIP Ecosystem Forum & Technology Symposium 23rd - 24th July, Amsterdam


2018 TSMC Israel Technology Workshop 5th September, Herzliya, Israel

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