Moortec’s Malcolm Gillett will present a paper entitled “A Layout Methodology for Deep Sub-Micron Technologies” during the CDNLive event in Munich on Tuesday 8th May at 14:00.
Malcolm is a Senior Analogue Layout Designer at Moortec and has Nearly 40 years’ experience of layout design within the industry, twenty-five of which were spent successfully running his own company, operating as a consultant providing additional layout resource to companies across Europe.
Based on our recent design experience using deep sub-micron processes at Moortec Semiconductors Ltd the following issues have had to be addressed:
1. An exponential increase in the number of Design Rule constraints.
2. Min & Max density requirements for different sized windows at local block & chip level.
3. The Layout Dependent Effects of Full-Custom analogue design productivity.
4. Colouring for 16nm & 7 nm processes.
1. A tile-based methodology that generates layouts DRC clean by construction.
2. Mitigates and controls layout dependent effects.
3. Improves Layout quality and efficiency.
4. Reduces the amount of layout resource required.
5. Reduces the number of layers the designer has to interact with
6. Maximises DFM & Recommended Rule usage.
1. The design phase is greatly simplified which improves layout efficiency.
2. Quality and reliability are improved.
3. Extract and simulation which take ‘fill’ into account at an early stage provides improved correlation and yield.
4. There is also potential for some macro blocks to be re-used across the companies range of temperature sensors, voltage monitors etc.
CDNLive EMEA brings together Cadence® technology users, developers, and industry experts for networking, sharing best practices on critical design and verification issues, and discovering new techniques for designing advanced silicon, SoCs, and systems.
The event is taking place from the 7th to the 9th of May at the Infinity Hotel & Conference Resort in Munich.
Established in 2005 Moortec provides compelling embedded sub-system IP solutions for Process, Voltage & Temperature (PVT) monitoring, targeting advanced node CMOS technologies from 40nm down to 7nm. Moortec’s in-chip sensing solutions support the semiconductor design community’s demands for increased device reliability and enhanced performance optimization, enabling schemes such as DVFS, AVS and power management control systems. Moortec also provides excellent support for IP application, integration and device test during production.