Moore’s law looks set to continue for now, thanks to the commercialization of FinFET and FDSOI technologies. Planar nodes such as 40nm and 28nm have suffered from an increase in physical issues such as thermal management, headroom reduction, and process variability. The move to FinFET / FDSOI at the 16/14nmnm nodes and beyond will only increase the magnitude of these issues. Gate density is the major contributor to thermal issues, IR drop issues are a result of the interconnect thickness and pitch, i.e., an increase in resistance per um length of interconnect.
In a thermal context, gate density equates to power density and in turn, localised thermal issues. Only accurate core temperature sensors placed near to potential hot spots provide the system with sufficient feedback to implement a dynamic control scheme for clock speed or supply. Energy Optimisation Systems (EOS) such as DVFS are becoming the big application area for on-chip PVT monitors as you can then performance optimise on a per chip basis.
In terms of IR Drop, as the gate density increases and the impedance of metal tracking for supplies increases, together with reduced headroom due to supply reduction, we’re seeing a greater problem for advanced nodes. Using on-chip core voltage supply monitors allows chip developers to see what the supply conditions are really like and how this compares to simulation results. In addition, when data outputs from these monitors are included in the architectural level of a SoC, the power supplies can be optimised for better performance, or power saving, as required. We can only see demand for such monitors increase as we move down the technology curve.
So the blessing from increased density is the wonderful technology that we all enjoy today, unimaginable only 10 years ago. The curse is the reliability effect of hotspots or the poor performance through IR drops. The consequential physical effects of increased gate density will ultimately be applying the brakes to Moore’s law.