Established in 2005 Moortec provides compelling embedded subsystem IP solutions for Process, Voltage & Temperature (PVT) monitoring, targeting advanced node CMOS technologies from 40nm down to 5nm. Moortec’s in-chip sensing solutions support the semiconductor design community’s demands for increased device reliability and enhanced performance optimization, enabling schemes such as DVFS, AVS and power management control systems. Moortec provides excellent support for IP application, integration and device test during production.
Moortec provide a complete PVT Subsystem on 40nm, 28nm, 16nm, 12nm, 7nm & 5nm which also includes a sophisticated PVT-Controller with AMBA APB interfacing. Along with our offering we can provide expertise on macro placement, production results support and guidance on how to implement DVFS, AVS optimisation schemes and reliability schemes. As a big growth area for advanced technology design, Moortec are able to help our customers understand more about architecting and implementing such schemes. Being the only dedicated PVT IP vendor, Moortec is now considered a centre-point for such expertise.
Since the beginning of the semiconductor industry, we have relied on a doubling of transistor count per unit area every 18 months as a way to increase performance and functionality of devices. Since 28nm, this has broken. As such, designers now need to find new ways to continue increasing performance.
Accurate PVT monitors are key to implementing die optimisation. We all know the relationship between power consumption and supply voltage of CMOS logic. Being able to reduce the supply by even a few percent based on that particular die’s process point, also combined with the environmental conditions that allow, will result in power savings worth having. The same is true with performance, if a given clock speed can be met with a lower supply. But none of this is possible if the monitors are not accurate.
Gate density has been increasing with each node and that pushes up power per unit area. This has become an even more significant issue with FinFET processes, where the channels are more thermally isolated than planar processes before them.
Then there is leakage, which in the last few planar nodes was an issue that led to significant power consumption. That has been pegged back somewhat with the latest FinFET nodes but it will continue to be an issue going forward as we look toward the next generation FinFET nodes and beyond.
A number of years ago when we started developing temperature sensors, they were being used generally just for device characterisation, HTOL, burn in tests and those kind of things. Then they started to be used for high temperature alarms, either to switch off the device or turn on a fan. But we have seen over the last couple of years more applications which rely on these monitors. Applications like Dynamic Voltage and Frequency Scaling (DVFS), Adaptive Voltage Scaling (AVS) and lifetime reliability. These applications make use of the sensor data in a feedback control loop. So certainly the use cases now are much more varied.
The supplies have been coming down, quicker than the threshold voltages which has led to less supply margin. In addition to this the interconnects are becoming thinner and closer together which is pushing up resistance and also capacitance. Compounding all of this is the usual increase in gate density seen with moving down the process nodes, which increases power per unit area.
Semiconductor devices age over time, we all know that but what is often not well understood are the mechanisms for ageing or the limits that will cause a chip to fail. In addition, there is bound to be a requirement for a minimum lifetime of a device which will depend on application but could be two or three years for a consumer device and up to twenty-five years for a telecommunications device. Given that lifetime requirement and often poorly understood ageing processes, many chips designed today are over designed to ensure reliable operation. If you understand that ageing process or better still can monitor the ageing process then you can reduce the over design and potentially even build chips that react and adjust for the ageing effect, or predict when that chip is going to fail.
From Moortec’s perspective we are working on monitors that can be used to measure the ageing process of a device in the field, by having reference structures and comparing them to live structures, we can compare the two over time. This is one application that is being used at the moment, alongside using the information to adjust the supply to bring the chip back to the performance level that you expect, or need. This is actually quite common, particularly in devices where there is a requirement for a particular throughput.
A closed loop AVS system uses certain structures within the chip to provide the data required to adaptively track the behaviour of the silicon. By using a delay chain that has the same operating voltage as the surrounding chip, the voltage frequency relationship for the chip for that frequency is calculated by measuring the frequency of the delay chain.
Using these schemes in-chip means that variations in response to process can be compared and fluctuations in temperature can be monitored while the chip is operating. A relationship can then be observed between voltage-frequency and the reduction in power dissipation for the circuit under that specific condition which enables designers to push the levels of optimisation and reliability, allowing them to get as much performance out of the chip as possible.
Process variation is a complex subject which covers a range of effects, but broadly we can consider that the effects are caused by imperfections in the manufacturing process. Examples are implant variations, mask misalignments, and optical variations. These all add up to give statistical variation on the ideal or “typical” transistor.
However, the mechanisms and causes of the variation are not particularly our concern. What we are interested in is being able to measure in a meaningful way where a particular piece of silicon is within the defined process space for the technology being utilised.
Process variability has always been an issue and the design process has taken account of the variability, often by designing for worst case. Whilst this is still possible doing so is eroding a larger proportion of the gains made by migrating to an advanced node and when this is coupled with additional sensitivities to supply voltage (an effect of the dropping of core supplies) we are at a point now where process variation and specifically, designing for worst case is too high.
Furthermore, with the advent of FinFET processes, and the fabrication methods to allow for the densities seen on current leading nodes, the process variation is manifesting itself in different ways. Due to the limited availability of production data on these nodes it is too early to say we fully understand process variation.