With the growth in the IoT market we are starting to see an increase in the number of wireless devices. The majority of these devices will be on older process nodes, however, the same performance gains can be found on these nodes. These devices will typically be battery powered and sensitive to power consumption. Because of this there will be a drive to improve efficiency in these products rather than perhaps improving performance, but they are different names for essentially the same problem. By understanding where a given die is with respect to process, voltage, and temperature, a more optimum solution can be found, whether that optimum solution is measured by performance or efficiency doesn’t matter.
At the same time we also have to consider automotive, which is a big growth area for the semiconductor industry as a whole. With the growth of the Advanced Driver Assistance Systems (ADAS) and Infotainment areas we will see more advanced nodes being used, certainly down to 28nm in the near future. Ideally some of these products would be on more advanced nodes but those are not qualified for automotive. As a result, the available technologies will have to be squeezed by designers to get the extra level of performance. In addition, the environment in automotive is harsh. So when you look at all of these factors together it is clear there is definitely room for die optimisation.
Accurate PVT monitors are key to implementing die optimisation. We all know the relationship between power consumption and supply voltage of CMOS logic. Being able to reduce the supply by even a few percent based on that particular die’s process point, also combined with the environmental conditions that allow, will result in power savings worth having. The same is true with performance, if a given clock speed can be met with a lower supply. But none of this is possible if the monitors are not accurate.
By being aware of a devices thermal and voltage environment and understanding where a given device is within the ever increasing sphere of device variation, allows the system architects and circuit designers to get more from a given piece of silicon. With the increase as well in the cost of advanced nodes, this is becoming even more important to ensure every last drop of performance is extracted from a die.
In-chip PVT monitoring is here now and it is here to stay. The costs of advanced node technologies are continuing to increase, and we are already starting to see a fragmentation, with the really advanced nodes becoming more niche for those devices which really need the performance. For those nodes, optimisation will be part of the architecture to ensure the cost of those expensive technologies is minimised. As the rest of the industry moves down to smaller nodes, they will look to differentiate their products from their competitor and good die optimisation will play a part in that.
So in answer to the question “Is PVT monitoring only a requirement for the advanced nodes?” The answer has got to be no, PVT monitoring is fast becoming an essential part of applications that may not necessarily have reached the advanced nodes but still have a critical requirement for performance optimisation and reliability.
Moortec provide a complete PVT Monitors on 40nm, 28nm, FinFET & 7nm which also includes a sophisticated PVT-Controller with AMBA APB interfacing. Along with our offering we can provide expertise on macro placement, production results support and guidance on how to implement DVFS, AVS optimisation schemes and reliability schemes. As a big growth area for advanced technology design, Moortec are able to help our customers understand more about architecting and implementing such schemes. Being the only PVT dedicated IP vendor, Moortec is now considered a centre-point for such expertise.
For more information please visit www.moortec.com