Moortec engineers have extensive background in high performance analog and RF IC design on BiCMOS technologies and CMOS technologies from 0.6um down to 40nm. We have a proven track record in low phase noise PLL, oscillator, ADC and DAC design.
- Low jitter PLLs (<1ps rms jitter)
- Flexible, low power PLLs with integrated loop filter (<10ps rms jitter)
- Crystal oscillators -150dBc @ 10kHz
- Embedded / On-Chip Temperature Sensors
- Power management e.g. Voltage regulators
- Power on reset
- ESD Design and implementation
- Special IOs e.g. SERDES, PCI, USB
- Low noise amplifiers (RF, baseband, fully differential op-amp)
- CMOS Band Gap voltage reference
- Wideband VCO's (up to 6GHz) cross coupled and Colpitts using on chip inductor
Low Phase Noise PLL Design:
We are experts in robust transistor level analogue / RF IC design, ultra low power sub-threshold design techniques and also mixed-signal verification. We are able to simulate and prove complex designs through an approach of modelling circuits in Verilog-A and VHDL-A. By adopting advanced verification methodologies we are able to functionally verify large mixed-signal designs in a timely manner, ensuring right-first-time silicon.