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In-Chip Performance Optimisation – Things to Consider when choosing a PVT Subsystem

With advances in CMOS technology and the scaling of transistor channel lengths down to nanometer (nm) dimensions, the density of digital circuits per unit area of silicon has increased, as has the process variability of devices manufactured. This increase in digital logic (or gate) density equates to an increase in power density which is a major contributor to the heating of advanced node CMOS semiconductor devices.

The combined effect of this increased logic gate density, increased track and via impedances and process variability has led to significant voltage (IR) drops across devices. Together with an increasingly noisy environment, the need to monitor on-chip conditions has become highly desirable to ensure that operating conditions are optimal within the complex systems in today’s devices.

In-chip process, voltage and temperature (PVT) monitoring is used for performance optimisation, an example being for the use in Dynamic Voltage and Frequency Scaling (DVFS) schemes where the system clock and supply voltage can be varied to optimise either for the speed of logical operations or for power consumption of the device.

A statistical analysis of each device would show a process variability, or spread, that when compared to historical CMOS technologies is wider (worse) for advanced technology nodes. The move to FinFETs at the 16, 12 and 7nm nodes has increased the magnitude of these issues. To address this, manufacturers have had to start designing their SoCs to over-compensate for the unwanted variabilities arising from the manufacturing process.

The traditional methodology of designing for worst case corners to cover process and supply variability is becoming increasingly wasteful. Hence, interest within the semiconductor community is growing for on-chip monitoring and how this data can utilized for performance optimisation.

To help developers implement monitoring and optimization schemes the following points should first be considered by developers and architects.

Define your requirement – Why are you interested in embedded in-chip monitoring?

  • To optimise power usage to maximise battery life?
  • To optimize performance for data throughput? (Often this is really data throughput per watt)
  • For ensuring device reliability? A key concern on advanced nodes is the reliability hit caused by electromigration and how this can be mitigated by maintaining optimal operating conditions.

Have you defined your parameters for optimal device operation?

  • What are the ideal on-chip conditions in terms of temperature and voltage supply to achieve required performance and device lifetime?
  • What are the acceptable limits around the ideal conditions under which the performance can be varied?
  • Can your production test strategy incorporate an assessment of the manufactured silicon in order to defined the parameters to each device?

Can you rely on your embedded monitors?

  • On-chip monitors have become critical components to ensure safe operation through the lifetime of the device. Accuracy and reliability of the monitors has to be a ‘given’ if they are to form the basis to a DVFS scheme.
  • Check the production testability of each monitor.
  • Can the monitor self-check during the devices lifetime?

What is your placement strategy?

  • Carefully consider where to place your monitors throughout your device.
  • Temperature sensors can be placed near to potential hotspots on the die, which can be identified through thermal analysis.
  • Circuits associated with hotspots will suffer from reduced lifetimes which can be problematic for silicon devices used in long-lifetime applications such as telecommunications products. Localised heating can produce elevated temperatures gradients of up to 30°C!
  • Supply monitors can be connected to the supply domains of interest throughout the architecture.
  • Process monitors can be scattered depending on the suspected level of process variability to see across a die. This will be dependent on the process node being used and can vary significantly between 40nm and FinFET for example. The process monitors selected should be resilient to process variability.

To fully capitalise on the benefits of an In-Chip Monitoring Subsystem, the circuits should be easy to integrate, be accurate, have high yield, have simple/quick calibration schemes in production (if calibration is required), use standard CMOS processes, convenient digital interfaces, IP must have expected deliverables and be ‘design-clean’ against the DRC/LVS decks from the latest available PDK.

By addressing these points raised, you should be some way to a successful implementation of an in-chip monitoring subsystem and performance optimization scheme. The opportunity is to mitigate the growing issues presented by advanced CMOS nodes of increased physical issues such as thermal management, headroom reduction, and process variability. In-Chip performance monitoring and control will help to increase, on a per-chip basis, the power efficiency, performance and reliability of advanced silicon devices in today’s electronics products.